采用硅通孔(TSV)技术的三维堆叠封装,是一种很有前途的解决方案,可提供微处理器低延迟,高带宽的DRAM通道。然而,在3D DRAM电路中,大量的TSV互连结构,很容易产生开路缺陷和耦合噪声,从而导致了新的测试挑战。通过大量的模拟研究,本文模拟了在三维DRAM电路的字线与位线中出现的TSV开路缺陷的故障行为,它作为有效测试和诊断这种缺陷方法的第一步。 A three-dimensional stacked package with through-silicon vias (TSVs) is a promising solution for providing microprocessors with low-latency, high-bandwidth DRAM channels. However, in 3D DRAM circuits, a large number of TSV interconnects are prone to open defects and coupling noise, leading to new test challenges. Through a large number of simulation studies, this paper simulates the fault behavior of open TSV defects in the word lines and bit lines of 3D DRAM circuits as a first step in an effective method of testing and diagnosing such defects.