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垂直注入逻辑(VIL)是集成注入逻辑(I~2L)的一种新形式。它采用垂直的p-n-p晶体管来代替横向p-n-p晶体管,在同样组装密度下能比普通I~2L获得更好的性能。由于p-n-p晶体管的电流增益可以提高,从而大大减小了功耗-延迟乘积。鉴于把底部注入器当作了空穴的俘获中心,使得本征延迟时间得到改善。本文叙述了VIL的工艺过程和它的电特性,并与普通I~2L作了比较,此外,还提出了一个实验性空穴俘获中心模型。实验结果表明在小于1μW的低功耗条件下VIL的最小延迟时间为8.8ns,功耗-延迟积为0.07 pJ,而标准I~2L则为25 ns和0.18 pJ。
Vertical Injection Logic (VIL) is a new form of integrated injection logic (I ~ 2L). It uses vertical p-n-p transistor instead of lateral p-n-p transistor, in the same assembly density can get better performance than normal I ~ 2L. As the p-n-p transistor current gain can be increased, thus greatly reducing the power - delay product. Due to the fact that the bottom injector is the hole trapping center, the intrinsic delay time is improved. This article describes the process of VIL and its electrical characteristics, and compared with the general I ~ 2L, in addition, also proposed an experimental hole trapping center model. The experimental results show that the minimum delay time of VIL is 8.8ns under low power consumption of less than 1μW, the power-delay product is 0.07 pJ, while the standard I ~ 2L is 25ns and 0.18 pJ.