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一、引言Viterbi 算法是一种有效的纠错译码算法,它具有显著的检错和纠错能力。但由于算法复杂、运算量大,长期以来很难应用于高速实时处理系统。近年来,随着微处理机技术的发展和数字信号处理技术的广泛应用,涌现出许多高速专用数字信号处理器,这些高速专用芯片的出现使Viterbi 译码用于高速实时处理系统的设想得以实现。在高速数据传输中,采用格状编码和Viterbi 译码相结合的技术可以在不降低传信率、不增加带宽的情况下有效地改善系统的误码性能。本文针对格状编码调制中采用Viterbi 译码时可能遇到的问题进行了分析,提出了解决方法并在此基础上提出一种用高速专用信号处理器TMS 32010实现9600 bit/s Modem 中的Viterbi 译码器的设计方案。同时进行了软、硬件设计。
I. Introduction Viterbi algorithm is an effective error correction decoding algorithm, which has significant error detection and correction capabilities. However, due to the complexity of the algorithm and the large amount of computation, it has been difficult to apply it to high-speed real-time processing systems for a long time. In recent years, with the development of microprocessor technology and the extensive application of digital signal processing technology, many high-speed dedicated digital signal processors have emerged. The advent of these high-speed dedicated chips has enabled Viterbi decoding to be used in high-speed real-time processing systems . In high-speed data transmission, the combination of Trellis coding and Viterbi decoding can effectively improve the BER performance of the system without reducing the signaling rate or increasing the bandwidth. In this paper, the problems that may be encountered when using Viterbi decoding in trellis-coded modulation are analyzed, and a solution is proposed. Based on this, a high-speed dedicated signal processor TMS32010 is proposed to realize Viterbi in 9600 bit / s modem Decoder design. At the same time a software and hardware design.