A design of a replica bit line control circuit to optimize power for SRAM is proposed.The proposed design overcomes the limitations of the traditional replica bit line control circuit,which cannot shut off the word line in time.In the novel design,the delay of word line enable and disable paths are balanced.Thus,the word line can be opened and shut off in time.Moreover,the chip select signal is decomposed,which prevents feedback oscillations caused by the replica bit line and the replica word line.As a result,the switch power caused by unnecessary discharging of the bit line is reduced.A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process.The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM,and their performances are compared with each other.The experimental results show that at a supply voltage of 1.2 V,the switch power consumption of the memory array can be reduced by 53.7%. A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which can not shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced .hus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.