With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger’s safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a new effective method which is based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy(HDDR) method, the original controller is quadruplicated and correct values are voted through the comparator and error detection unit. We have analyzed the proposed system with Reliability, Availability, Mean time to failure and Security(RAMS) theory in order to evaluate the effectiveness of proposed scheme. Theoretical analysis shows that the Mean Time To Failure(MTTF) of the proposed system is 2.5 times better than the traditional Triple Modular Redundancy(TMR). Furthermore, the fault injection experimental results reveal that the capability of tolerating Single Event Upsets(SEUs) in the proposed method increases up to 7.5 times with respect to a regular speed controller. With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger’s safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy (HDDR) method, the original controller is quadruplicated and correct values ​​are voted through the comparator and error detection unit. We have analyzed the proposed system with Reliability, Availability, Mean time to failure and Security (RAMS) theoretical in order to evaluate the effectiveness of proposed scheme. Theoretical analysis shows that the Mean Time To Failure (MTTF) of the proposed system is 2.5 times better than the traditional Triple Modular Redundancy (TMR). Furthermore, the fault injection experimental results reveal that the capability of tolerating Single Event Upsets (SEUs) in the proposed method increases up to 7.5 times with respect to a regular speed controller.