提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它可以工作到1.6Gb/s .芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s ,同时发送和接收端的功耗分别是35和6 mW. A high-speed, low-power low-voltage differential interface circuit is proposed, which can be used in chips that need high-speed interface such as CPU, LCD, FPGA, etc. At the transmitting end, a stable reference voltage and common-mode feedback circuit are applied to low voltage differential Circuit, it enables the transmitter to overcome power, temperature, and process-induced waveform changes. The receiver uses a rail-to-rail amplifier architecture that can operate up to 1.6Gb / s. The chip design uses a 0.18μm CMOS process The chip test results show that the data transmission rate of the entire sending and receiving end can reach 1.6Gb / s, and the power consumption of the sending and receiving ends is 35 and 6 mW respectively.