A 2.5 GS/s 14-bit D/A converter with 8 to 1 MUX

来源 :Journal of Semiconductors | 被引量 : 0次 | 上传用户:gf_lucky
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A 2.5 GS/s 14-bit D/A converter(DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a “5+9”segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT(process, source voltage and temperature) corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a “5-31”decoder is used to improve the DAC’s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer(DDS) chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm~2 including bond pads(DAC only), and the measured performance is SFDR > 40 d B(with and without DEM) for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure(means return-to-zero or quad-switch structure is unutilized),this paper DAC’s clock frequency(2.5 GHz) and higher output frequency SFDR(> 40 d B, up to 1 GHz) has some competition. A 14-bit D / A converter (DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a “5 + 9” segment PMOS current-steering architecture. PMOS current source supply a larger output impedance under every PVT (process, source voltage and temperature) corner is also presented. A811 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. which is merged with a “5-31 ” decoder is used to improve the DAC’s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer (DDS) chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm ~ 2 including bond pads (DAC only), and the measured performance is SFDR> 40 d B with and without DEM for output signal frequency up to 1 GHz. Compared with other presented published DACs with a non- analog-resample structure (means return-to-zero or quad-switch structure is unutilized), this paper DAC’s clock frequency (2 .5 GHz) and higher output frequency SFDR (> 40 d B, up to 1 GHz) has some competition.
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