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基于0.18μm SiGe BiCMOS工艺,设计了一种用于10位200 MHz高速流水线模数转换器的CMOS LVDS收发电路。该收发电路由发射器(TX)和接收器(RX)组成。发射器通过带共模反馈的闭环控制电路,将0~3.3 V的CMOS信号转换成(1.2±0.35)V的LVDS信号。接收器采用一个轨至轨预运算放大器保证LVDS信号的完整接收,并实现一定的增益,之后由迟滞比较器和输出缓冲器实现对共模噪声的抑制以及信号驱动能力的提高,最终正确恢复出CMOS信号。仿真结果表明,在400 MHz脉冲输入下,收发器可以稳定工作在3.3 V电源电压,总功耗仅为22.4 mW。
Based on the 0.18μm SiGe BiCMOS process, a CMOS LVDS transceiver circuit designed for 10-bit 200 MHz high-speed pipeline A / D converter is designed. The transceiver circuit consists of transmitter (TX) and receiver (RX). The transmitter converts a 0 ~ 3.3 V CMOS signal into an LVDS signal of (1.2 ± 0.35) V through a closed loop control circuit with common mode feedback. The receiver uses a rail-to-rail pre-operational amplifier to ensure complete reception of the LVDS signal and to achieve a certain gain, followed by the hysteresis comparator and the output buffer to achieve suppression of common-mode noise and signal-driven ability to improve, the final correct recovery CMOS signal. The simulation results show that the transceiver can operate stably at a 3.3 V supply voltage with a total power consumption of only 22.4 mW at 400 MHz pulse input.