为了避免时延故障测试因额外测试器插入导致过高的硬件成本和性能降低,本文提出了一种内建自测试测试向量生成器设计.该方案通过对累加器结构作低成本的设计改进,并通过一种高效的单跳变序列生成算法设计了时延故障测试序列生成器.该设计改动微乎其微,通过将原有加法单元替换为一种改进的加法单元,对加法器原有关键通路无任何额外的时延影响.该累加器可执行通常的累加运算,在测试时又可担当测试器.与以往的方法相比,具有两个显著优点:低的硬件成本及低的时间开销.由于累加器在VLSI电路中普遍存在,本文的复用设计节省硬件成本,可有效用于强健时延故障的测试序列生成.“,”A novel built-in self-test (BIST) test pattern generator (TPG) was designed in order to avoid much hardware overhead and performance degradation when additional TPG was inserted for delay fault test. In this scheme, a TPG is designed by a low cost structural modification of an accumulator with an algorithm for single input change test sequence generation. The modification was nearly negligible in which the full adder cells are substituted by cells termed modified full adder and such design has not any additional delay effect on the original critical paths inside the adders. The accumulator can perform normal accumulation and act as TPG when test is needed. Compared with previous scheme, the proposed had two merits of low hardware overhead and low time cost. As accumulators are available in many VLSI circuits, such reuse design can save much hardware cost and be adopted effectively as BIST test pattern generator for robustly delay fault testing.