阐述了一种基于VHDL实现的快速位同步方案,改进了传统的超前-滞后型数字锁相环(LL-DPLL)提取位同步信息的方法,使得同步捕捉时间极大地缩短,在最坏条件下位同步捕捉时间将比传统方法快数十倍.简要地分析了该位同步实现方案的各项基本性能,并以实验测试验证了设计原理. This paper presents a fast bit synchronization scheme based on VHDL, which improves the method of extracting bit synchronization information from traditional lead-lag type digital phase-locked loop (LL-DPLL), which greatly shortens the synchronization capture time. Under the worst condition bit Synchronous capture time will be ten times faster than the traditional method.A brief analysis of the basic performance of the bit synchronization scheme, and experimental design to verify the principle of the experiment.