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为了在薄埋氧层SOI衬底上实现超高耐压LDMOS铺平道路,提出了一种具有P埋层(BPL)的薄埋氧层SOI LDMOS结构,耐压1200V以上。该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层。当器件正向截止时,N型漂移区与P埋层之间的反偏PN结将承担器件的绝大部分纵向压降。采用2维数值仿真工具Silvaco TCAD对BPL SOI LDMOS进行虚拟制造和器件仿真,结果表明该结构采用适当的参数既能实现1 280 V的耐压,将BOL减薄到几百纳米以下又可以改善其热特性。
In order to pave the way for ultra-high-voltage LDMOS on SOI substrate, a buried oxide SOI LDMOS structure with P buried layer (BPL) is proposed, with a withstand voltage of over 1200V. The BPL SOI LDMOS introduces a P-type buried layer between the buried oxide and N-type drift regions of a conventional SOI LDMOS. The reverse bias PN junction between the N-type drift region and the P buried layer assumes the most part of the device’s longitudinal voltage drop when the device is normally turned off. Silvaco TCAD, a two-dimensional numerical simulation tool, was used to simulate the fabrication and device simulation of BPL SOI LDMOS. The results show that the structure can withstand 1,280 V with suitable parameters and thinner to several hundreds of nanometers Thermal characteristics.