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功耗分析是低功耗逻辑综合的一个重要步骤。ＣＭＯＳ组合逻辑电路的功耗分析由于电路节点之间存在相关性而变得复杂。采用两两相关的方法对电路内部节点的相关性进行建模，并且对相关性进行划分强弱分别进行处理，从而提高了计算的精度。同时为了降低计算的空间复杂度，对电路采用了按逻辑深度分级计算的方法，使计算的复杂度并不与电路规模直接相关。对ＩＳＣＡＳ’８５基本测试电路（ｂｅｎｃｈｍａｒｋ）的实验结果说明此方法可以有效地用于较大规模的组合逻辑电路的功耗分析。
Power analysis is an important step in low-power logic synthesis. Power analysis of CMOS combinational logic circuits is complicated by the correlation between circuit nodes. The two-to-two correlation method was used to model the relativity of internal nodes in the circuit, and the strength of the correlations was separately processed, which improved the accuracy of the calculation. At the same time, in order to reduce the computational space complexity, the method of hierarchical calculation by logic depth is applied to the circuit so that the computational complexity is not directly related to the circuit scale. The experimental results of ISCAS’85 basic test bench show that this method can be effectively used for the power consumption analysis of larger scale combinational logic circuits.