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Ｔｉｇｅｒ可以完成从布局到详细布线的整个布图全过程。在整个布图过程中，根据ＲＣ延迟模型计算所有连线的延迟，并把整个芯片的时延最小作为优化目标。在Ｔｉｇｅｒ系统中，应用了性能驱动的布局和总体布线算法、ＤＲＡＦＴ通道布线算法和基于垂直通道模型的走线道分配算法。实验结果表明，Ｔｉｇｅｒ的布图速度要比ＴｉｍｂｅｒＷｏｌｆ６．０快很多。它在保证芯片性能的同时，其芯片面积与ＴｉｍｂｅｒＷｏｌｆ差不多。
Tiger can complete the entire layout from the layout to the detailed layout of the entire process. Throughout the layout process, according to the RC delay model to calculate the delay of all connections, and the entire chip delay as the optimization goal. In the Tiger system, a performance-driven layout and overall routing algorithm, a DRAFT channel routing algorithm and a vertical channel model-based routing algorithm are applied. Experimental results show that Tiger’s layout speed is much faster than TimberWolf6.0. It guarantees the chip performance at the same time its chip area and TimberWolf almost.