本文提出了ＭＰＥＧ２视频解码器主要功能模块的专用ＶＬＳＩ结构．其中包括一种新的适用于ＭＰＥＧ２标准的ＩＤＣＴ实现方法，对于８点一维ＩＤＣＴ，只用７个变量乘常系数乘法器和１０个加／减法器，在４个时钟周期内能处理完８点数据；通过合理分配画面存储结构，提出了一种新的流水线的运动补偿预测结构．用ＶＨＤＬ语言进行仿真，并用１．０μｍＣＭＯＳ单元库进行综合，满足ＭＰＥＧ２ＭＰ＠ＭＬ视频解码的实时处理要求 This text has proposed the specialized VLSI structure of the main function module of MPEG2 video decoder. This includes a new IDCT implementation for the MPEG2 standard. For 8-point 1D IDCTs, only seven variables are multiplied by a constant coefficient multiplier and 10 adder / subtracters to handle 8 in 4 clock cycles Point data; through the reasonable allocation of the picture storage structure, a new pipeline motion compensation prediction structure is proposed. Simulation with VHDL language and synthesis with 1.0μm CMOS cell library to meet the real-time processing requirements of MPEG2MP @ ML video decoding