系统设计师必须考虑加电和断电期间芯核电源和 I/O 电源之间的定时差和电压差(换言之。就是电源定序)问题。当电源定序不当时。就有可能发生闭锁失灵或电流消耗过大的现象。如果两个电源加到芯核接口和 I/O 接口上的电位不同时,就会出现触发闭锁。定序要求不相同的 FPGA 和其他元件会使电源系统设计更加复杂化。为了排除定序问题,你应当在加电和 The system designer must consider the timing and voltage differences (in other words, sequencing) between the core and I / O supplies during power-up and power-down. When the power sequencing is not correct. It is possible to lock failure or excessive current consumption phenomenon. If both power supply to the core interface and the I / O interface, the potential difference occurs when the trigger lock. FPGA and other components with different sequencing requirements can complicate the power system design. In order to rule out the sequencing, you should be at power-up