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5. STATE VERIFICATION FOR SYNCHRONOUS CIRCUITS

STATE VERIFICATION FOR SYNCHRONOUS CIRCUITS

来源 :Journal of Electronics(China) | 被引量 : 0次 | 上传用户：belive

【摘 要】

：

This paper presents the techniques of implicit traversing and state verification for sequential finite state machines(FSMs) based of on the state collapsing of

【出 处】

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Journal of Electronics(China)

【发表日期】

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1997年2期

【关键词】

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VERIFICATION ENUMERATION STATE transition graph BINARY DECISION DIAGRAM Verifica 

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This paper presents the techniques of implicit traversing and state verification for sequential finite state machines(FSMs) based of on the state collapsing of state transition graph(STG). The problems of state designing are described. In order to achieve

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