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在解释了传统基本两级CMOS运算放大器低电源抑制比(PSRR)原因的基础上,提出了一种简单电路技术来提高传统基本两级CMOS运算放大器中频PSRR。该方法原理是通过改变偏置结构产生一个额外的信号支路在输出端跟随电源增益,这样在输出端可以得到近似为零的电源纹波增益,从而能提高运放的PSRR。采用0.35μm标准CMOS工艺库,在Cadence环境下仿真结果显示,改进的运算放大器的PSRR在中频范围内比传统运算放大器可提高20dB以上。
Based on the explanation of the reason of low power supply rejection ratio (PSRR) of the traditional two basic CMOS op amps, a simple circuit technique is proposed to improve the mid-frequency PSRR of the traditional two basic CMOS op amps. The principle of this method is to generate an extra signal branch by changing the bias structure to follow the power gain at the output so that a nearly zero supply ripple gain can be achieved at the output to improve the op amp PSRR. Using 0.35μm standard CMOS technology library, the simulation results in Cadence environment show that the PSRR of the improved operational amplifier can be increased by more than 20dB over the traditional operational amplifier in the intermediate frequency range.