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本文介绍了一种新型的32位浮点(IEEE标准)DSP向量信号处理器的结构,其内部结构是高度并行的,它主要是由六个各自独立而很好配合的单元组成。它的ALU有一个流水线结构,此流水线结构对执行DSP和矩阵运算(特别对FFT的蝶式运算)是优化的。极为灵活的向量指令系统可以便其内部资源得到最有效的利用。所有这些特点便其成为高性能、大吞肚量的处理器,它具有31MFLOPS(百万次浮点运算/秒)的运算能力而额外开销极少。本文介绍这种器件的结构,介绍其内部各单元及其相互配合,还介绍指令系统的基本特点。本文给出单个处理器的一些基本性能指标。并提出一种简单的小系统结构,即把两个处理器组合在一起,共享单一总战,其吞吐率是单个处理器系统的两倍。
This article describes the structure of a new 32-bit floating-point (IEEE standard) DSP vector signal processor that is highly parallel in its internal structure and consists mainly of six distinct and well-coordinated units. Its ALU has a pipelined architecture that is optimized for DSP and matrix operations, especially for FFTs. Extremely flexible vector instruction system can be the most efficient use of its internal resources. All of these features make them high-performance, high-volume processors with 31MFLOPS (million floating-point operations per second) computing power with minimal overhead. This article describes the structure of this device, introduces its internal units and their mutual cooperation, but also introduces the basic characteristics of the command system. This article gives some basic performance indicators of a single processor. And proposed a simple small system structure, that is, the two processors together, sharing a single total war, the throughput rate is double the single processor system.