论文部分内容阅读
Ⅰ.引言在毫微秒数字逻辑系统的设计中,由于广泛地采用大规模集成(LSI)电路而引起了一些新的矛盾,特别是随着集成规模的增大,在保持高封装密度所具有的高速度优点的同时,有必要以较小的功耗来实现更复杂的逻辑功能。同时一个集成片的引线数,互连图案的复杂性,和扇入扇出的能力,也是对线路和逻辑设计者提出的一些限制。在资料[1]中已经提出用一种二级逻辑操作的结构可以满足上述要求,如果逻辑的完成是按输入变量到达的先后来划分,
I. INTRODUCTION In the design of nanosecond digital logic systems, new paradoxes have arisen due to the widespread adoption of large scale integrated circuits (LSIs), especially as the integration scale increases, while maintaining the high packing density While at the mercy of high speed, it is necessary to achieve more complex logic functions with less power consumption. At the same time, the lead count of an integrated chip, the complexity of interconnect patterns, and fan-in fan-out capabilities are also some of the limitations imposed on line and logic designers. In the data [1], it has been proposed to use a structure of two-level logic operations to meet the above requirements. If the completion of the logic is divided according to the order in which the input variables arrive,