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还需要一段时间才能有可信的运行经验和失效分析数据作为MOS/LSI(金属-氧化物-半导体/大规模集成)器件可靠性预测的基础。与此同时,可靠性工程师现今面临着需要对使用这些器件的设备进行可靠性予测。为了满足这个要求,已经提出了几种方法。通常是利用具有相似失效模式的其他微电子器件的经验。本文所提出的方法是基于对芯片线路结构的了解和评价,采用的程序是广泛应用的双极集成电路失效率计算方法的外推,该方法来源于罗马空军发展中心(RADC)可靠性说明书。为外推到MOS/LSI器件,引入了评价不同封装和线路复杂性的方法,以及如何把这些差别作为因子引进到予测程序中。该程序已凭经验加以调整,以使与已知的MOS/LSI失效率数据相吻合。这个方法是有效的、实际的和容易使用的,也是现在做得到的。
It will take some time for credible operational experience and failure analysis data to be used as a basis for reliability prediction of MOS / LSI devices. In the meantime, reliability engineers are now faced with the need to test the reliability of devices that use these devices. In order to satisfy this requirement, several methods have been proposed. It is often the experience to utilize other microelectronic devices with similar failure modes. The proposed method is based on the understanding and evaluation of the chip line structure. The procedure used is extrapolation of the widely used method for calculating the failure rate of bipolar integrated circuits. This method is based on the RADC reliability specification. For extrapolation to MOS / LSI devices, methods for evaluating different package and line complexity are introduced, and how these differences are introduced as factors into the predictive program. This program has been empirically adjusted to match known MOS / LSI failure rate data. This method is effective, practical and easy to use, and it is now possible.