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DRAM器件制造商通过缩小设计规则、芯片尺寸来提高存储器性能和密度的方法,正面临着众多挑战。增大电容面积,使用更高介电常数的材料,以及减薄介电材料厚度等方法都能够继续延续电容的形式和功能。多年以来,制造高深宽比(HAR)结构一直都是半导体工业所面对的一个难题。尽管如此,随着器件集成密度的不断提高,业界对于HAR图形的定义也不断发生着变化。大约5年前,最先进的HAR大概为20:1,用于1GB的存储器器件中。尽管如此,为了维持未来更高密度器件的电学性能,更高
DRAM device manufacturers are faced with a number of challenges by reducing design rules and chip size to improve memory performance and density. Increasing the capacitance area, using higher dielectric constant materials, and thinning the thickness of the dielectric material, etc. can continue to extend the form and function of the capacitor. Over the years, manufacturing high aspect ratio (HAR) structures has been a challenge for the semiconductor industry. However, as the device integration density continues to increase, the definition of HAR graphics in the industry continues to change. About 5 years ago, the state-of-the-art HAR was probably 20: 1 for 1GB of memory devices. However, in order to maintain the electrical performance of higher density devices in the future, it is even higher