基于并行分时A/D转换器的理论研究,对该类型A/D转换器进行了系统行为级设计和仿真。分析了系统中并行误差及流水线A/D转换器等误差源对整个系统性能的影响。通过计算机仿真,给出了系统模块的设计参数。通过理论分析与系统仿真,为并行分时流水线A/D转换器的设计提供了理论依据和数据参考,为该类型A/D转换器提供了设计优化方向。 Based on the theoretical study of parallel time-division A / D converter, the system-level design and simulation of this type A / D converter are carried out. The impact of parallel errors in the system and error sources such as pipeline A / D converters on overall system performance is analyzed. Through computer simulation, given the design parameters of the system module. Through theoretical analysis and system simulation, this paper provides a theoretical basis and data reference for the design of parallel time-division pipeline A / D converter, which provides the design optimization direction for this type of A / D converter.