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LZMA(Lempel Ziv Markov-chain Algorithm)无损压缩算法在进行数据压缩时速度慢且占用大量的CPU(Central Processing Unit)资源,不能满足实时系统的要求.在改进算法的基础上,采用FPGA(Field Programmable Gate Array)设计了一个LZMA压缩算法硬件加速电路.该电路由LZ77压缩控制器、区间编码控制器和数据读出控制器组成,采用数据乒乓结构、高性能并行匹配结构和流水线处理结构等多种方法提高了LZMA压缩算法的速度,在支持标准LZMA压缩文件格式的同时,将压缩速度提升到近125 Mb/s,相比基于软件的LZMA算法加速10倍,每个时钟处理的相对数据加速近200倍.最后通过基于Virtex-6 FPGA的ML605开发平台验证了硬件加速电路的正确性和可行性.
LZMA (lossless compression algorithm) can not meet the requirements of real-time system because it is slow and consumes a large amount of CPU (Central Processing Unit) resources during data compression.On the basis of the improved algorithm, Field Programmable Logic Device (FPGA) Gate Array), a hardware acceleration circuit of LZMA compression algorithm is designed.The LZ77 compression controller, interval code controller and data readout controller are used in this circuit, which adopt data ping-pong structure, high-performance parallel matching structure and pipeline processing structure etc. The method improves the speed of the LZMA compression algorithm. While supporting the standard LZMA compressed file format, the compression speed is raised to nearly 125 Mb / s, which is 10 times faster than the software based LZMA algorithm. The relative data processing speed of each clock is accelerated 200 times.Finally, we verify the correctness and feasibility of the hardware acceleration circuit through the ML605 development platform based on Virtex-6 FPGA.