2. 您的位置
3. 首页
4. 会议论文
5. An Effective Photoplethysmography Signal Processing System Based on EEMD Method

An Effective Photoplethysmography Signal Processing System Based on EEMD Method

来源 :2015 International Symposium on VLSI Design, Automation and | 被引量 : 0次 | 上传用户：tlihao

【摘 要】

：

This study proposed an effective signal processing system based on Ensemble Empirical Mode Decomposition EEMD method for the analysis of Photoplethysmography PP

【作 者】

：

Jia-Ju Liao Shang-Yi Chuang Chia-Ching Chou Chia-Chi Chang Wai-Chi Fang 

【机 构】

：

NationalChiaoTungUniversity,Taiwan

【出 处】

：

2015 International Symposium on VLSI Design, Automation and

【发表日期】

：

2015年4期

下载到本地 , 更方便阅读

下载此文 赞助VIP

声明 : 本文档内容版权归属内容提供方 , 如果您对本文有版权争议 , 可与客服联系进行内容授权或下架

论文部分内容阅读

This study proposed an effective signal processing system based on Ensemble Empirical Mode Decomposition EEMD method for the analysis of Photoplethysmography PPG.The whole system was implemented on an ARM-based SoC development platform to attain the on-line non-stationary signal processing.

其他文献

A Time Delay Integration CMOS Image Sensor with Online Deblurring Algorithm

会议

System-Level Test Coverage Prediction by Structural Stress Test Data Mining

会议

A Test-Application-Count Based Learning Technique for Test Time Reduction

会议

Hybrid Scrambling Technique for Increasing the Fabrication Yield of NROM-Based ROMs

会议

Clock-Domain-Aware Test for Improving Pattern Compression

会议

A Hybrid Built-In Self-Test Scheme for DRAMs

会议

TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for Cell-Internal Defects

会议

A 2.5 mW/ch, 50 Mcps, 10-Analog Channel, Adaptively Biased Read-Out Front-End IC with 9.71 ps-RMS Ti

会议

A Dual-Edge Sampling CES Delay-Locked Loop Based Clock and Data Recovery Circuits

This paper presents a dual-edge sampling clock-embedded signaling CES DLL based CDR.By combining the proposed dual edge sampling and half-UI embedded clock codi

会议

A High-PSRR ADPLL with Self-Regulated GRO TDC and DCO-Dedicated Voltage Regulator

This paper describes a PSRR enhancing method for the all-digital phase-locked loop ADPLL by utilizing a self-regulated gated ring-oscillator SR-GRO time-to-digi

会议