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This paper presents a low power 10 bit 300 ksps successive approximation register analog-to-digital converter(SAR ADC) which is applied in wireless sensor network(WSN) applications.A single ended energysaving split capacitor DAC array and a latch comparator with a rail to rail input stage are utilized to implement the ADC,which can reduce power dissipation while expanding the full scale input range and improve the signal-tonoise ratio(SNR).For power optimization the supply voltage of the SAR ADC is designed to be as low as 2 V.Four analog input channels are designed which make the ADC more suitable for WSN applications.The prototype circuit is fabricated using 3.3 V,0.35 μm 2P4 M CMOS technology and occupies an active chip area of 1.23 mm2.The test results show that the power dissipation is only 200 μW at a 2 V power supply and a sampling rate of166 ksps.The calculated SNR is 58.25 dB,the ENOB is 9.38 bit and the FOM is 4.95 pJ/conversion-step.
This paper presents a low power 10 bit 300 ksps successive approximation register analog-to-digital converter (SAR ADC) which is applied in wireless sensor network (WSN) applications. A single ended energysaving split capacitor DAC array and a latch comparator with a rail to rail input stage are utilized to implement the ADC, which can reduce power dissipation while expanding the full scale input range and improve the signal-tonoise ratio (SNR). For power optimization the supply voltage of the SAR ADC is designed to be as low as 2 V. Four analog input channels are designed which make the ADC more suitable for WSN applications. The prototype circuit is fabricated using 3.3 V, 0.35 μm 2P4 M CMOS technology and occupies an active chip area of 1.23 mm2. The test results show that the power dissipation is only 200 μW at a 2 V power supply and a sampling rate of 166 ksps. The calculated SNR is 58.25 dB, the ENOB is 9.38 bit and the FOM is 4.95 pJ / conversion-step.