针对一款双频双模导航基带芯片的ASIC设计,提出一种多异步时钟域的时序约束设计方法,并通过设置虚假路径、多周期路径和修正建立保持时间违例的方法,优化了时序。最终使芯片满足系统时序要求,通过了静态时序验证,为芯片流片提供了可靠保证。 Aimed at the ASIC design of a dual-band dual-mode navigation baseband chip, a time-constrained design method of multi-asynchronous clock domain is proposed. The timing is optimized by setting false paths, multi-cycle paths and revising the method of establishing the hold time violation. Eventually make the chip meet the system timing requirements, passed the static timing verification, to provide a reliable guarantee for chip streaming.