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文中提出了一种应用于10位逐次逼近ADC的比较器。该比较器包括预放大器、中间放大器、输出驱动级及共模电平缓冲器。整体开环设计,采用多级级联的形式以满足增益和速度的要求;采用输出失调消除技术进行失调校正;为了提高共模电平的驱动能力和缩短建立时间,采用分压电路加单位增益放大器的结构。基于3.3V电源电压、TSMC0.18μmCMOS工艺下,仿真结果表明,完全满足最高采样频率30MHz、10位精度的模数转换器要求。
This paper presents a comparator applied to a 10-bit successive approximation ADC. The comparator includes a preamplifier, an intermediate amplifier, an output driver stage, and a common mode level buffer. The overall open-loop design, the use of multi-level cascade to meet the requirements of gain and speed; using output offset cancellation techniques for offset correction; in order to improve the common-mode drive capability and shorten the settling time, the use of voltage divider circuit plus unity gain Amplifier structure. Based on the 3.3V power supply voltage and the TSMC 0.18μmCMOS process, the simulation results show that the ADC fully meets the requirements of analog-to-digital converter with maximum sampling frequency of 30MHz and 10-bit precision.