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快捷半导体公司的EnSigna实验室建模专家已经为其LVDS接口IC产品。开发出增强型IBIS模型产生方法。采用这种新方法可以提高LVDS IBIS模型精确度,从而提供可靠的仿真结果及实际相关性。 LVDS器件适用于通信、计算及悄费设露的多个底板及互联应用。LVDS器件具有高速互联性能,这是提高系统带宽的关键因素。这些应用需要高度准确的模型拍关性,以执行系统性能及进行系统优化。 由于LVDS I/O的特性不同,现有IBIS模型产生技术并不能说明补充输出结构的互相依赖关系。EnSigna工程师在HSPICE模型的LVDS器件外部增加了偏置元件,以确保每个互补输出的工作条件一致。在这些条件下获取的数据将用来生成IBIS模型。__ 设计工程师会在设计之前和设计过程中,利用LVDS IBIS模型进行器件和系统性能的验证,可有肋于他们优化系统性能,并同时降低风险、缩短产品投放市场时间。新的LVDS IBIS模型可以从EnSigna Lab及EnSigna Wab免费获取。更多信息请访问公司网站:www.fairchildsemi.com。
FastSignal’s EnSigna Laboratory Modeling Expert has been the LVDS Interface IC for its products. Development of an enhanced IBIS model generation method. Adopting this new method can improve the accuracy of the LVDS IBIS model, providing reliable simulation results and realistic correlation. LVDS devices are suitable for a variety of backplane and interconnect applications that require communication, computing and privacy. The high-speed interconnect performance of LVDS devices is a key factor in increasing system bandwidth. These applications require highly accurate model shotgap performance to perform system performance and system optimization. Due to the different characteristics of LVDS I / Os, the current IBIS model generation techniques do not account for the interdependencies of the complementary output structures. EnSigna engineers added biasing components to the HSPICE model’s LVDS devices to ensure the same operating conditions for each complementary output. The data obtained under these conditions will be used to generate the IBIS model. __ Design engineers validate device and system performance with LVDS IBIS models prior to and during design, allowing them to optimize system performance while reducing risk and reducing time-to-market. The new LVDS IBIS model is available free of charge from EnSigna Lab and EnSigna Wab. For more information, visit the company’s website at www.fairchildsemi.com.