论文部分内容阅读
针对现场可编程门阵列(FPGA)的布线拥挤问题,为了提高布通率,提出了基于异步串行链接的FPGA布线框架,该框架由异步串行收发器和相应的快速布线算法组成,最大优势是将串行线路的合理框架成功应用于FPGA。首先,在FPGA中添加异步串行收发器;然后,运用post-routing算法更新FPGA布线,选择非关键且足够长的导线段附近的最优组,对其进行串行化。最后,异步串行数据传输后,将信号反串行化成并行信号。实验结果显示,在面积和功耗的代价合理的情况下,利用异步数据串行化能有效减少布线数量和布线拥挤(分别为18.81%和48.73%),同时系统性能并未有任何下降。该算法可用于开发集成度更高、更复杂的FPGA。
In order to solve the problem of wiring crowding in field programmable gate array (FPGA), in order to improve the fabric pass rate, an FPGA based cabling framework based on asynchronous serial link is proposed. The framework consists of an asynchronous serial transceiver and a corresponding fast cabling algorithm. Is the successful application of a reasonable framework for serial lines to FPGAs. First, add an asynchronous serial transceiver to the FPGA; then, use the post-routing algorithm to update the FPGA cabling and select the best group near the non-critical and long enough wires to serialize it. Finally, asynchronous serial data transmission, the signal will be deserialized into parallel signals. Experimental results show that using asynchronous data serialization can effectively reduce the number of cabling and wiring crowding (18.81% and 48.73% respectively) at a reasonable cost of area and power consumption without any drop in system performance. The algorithm can be used to develop more integrated, more complex FPGAs.