详细分析了自偏置锁相环(PLL)的工作原理,采用一种新颖的折叠式电荷泵(CP)结构,包含一个宽摆幅电流镜,实现了更好的电流匹配,降低了PLL的系统抖动。该PLL采用130nm CMOS工艺进行制造。VCO的调频范围为0.43~1.54GHz。在1.25GHz工作频率下,频偏1 MHz处,PLL的相位噪声为-89.6dBc/Hz,均值抖动为3.03ps,峰峰值抖动为18.16ps,芯片面积仅为0.34mm2。 A detailed analysis of the operation of a self-biased phase-locked loop (PLL) employs a novel folded charge pump (CP) architecture that includes a wide swing current mirror for better current matching and reduced PLL System jitter. The PLL is fabricated in a 130nm CMOS process. VCO FM range of 0.43 ~ 1.54GHz. At a frequency of 1.25GHz, the phase noise of the PLL is -89.6dBc / Hz at a frequency offset of 1 MHz, with an average jitter of 3.03ps, a peak-to-peak jitter of 18.16ps and a chip area of ​​only 0.34mm2.