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In this paper,we present a graphics processing unit(GPU)-based implementation of a weighted bit-reliability based(wBRB)decoder for non-binary LDPC(NB-LDPC)codes.To achieve coalesced memory access-es,an efficient data structure for the wBRB algorithm is proposed.Based on the Single-In-struction Multiple-Threads(SIMT)program-ming model,a novel mapping strategy with high intra-frame parallelism is presented to improve the latency and throughput perfor-mance.Moreover,by using Single-Instruction Multiple-Data(SIMD)intrinsics,four 8-bit message elements are packed into a 32-bit unit and simultaneously processed.Experimental results show that the proposed wBRB decoder provides good tradeoff between error perfor-mance and throughput for the codes with rela-tively large column degrees or high rates.