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采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。
A 10-bit, 50-MHz, pipelined analog-to-digital converter is designed using a combination of 1.5 bits per level and 2.5 bits per level. Through the use of bootstrap switching and gain bootstrap foldable cascode op amp, guaranteed sample and hold circuit and circuit performance. The circuit uses CSMC 0.5μm 5 V CMOS process for layout design and chip verification, the chip area of 5.5 mm2. The test results show that the signal to noise ratio (SNDR) is 56.5 dB and the spurious-free dynamic range (SFDR) is 73.9 dB at a sampling frequency of 50 MHz and an input signal frequency of 30 kHz. With a 20 MHz input frequency, the signal plus harmonic distortion ratio is 52.1 dB and the spurious-free dynamic range is 65.7 dB.