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为了降低硬件成本和在较低频率下实现基于精简指令集计算机(reduced instruction set computer,RISC)处理器的先进音频编码(advanced audio coding,AAC),提出了一种软硬件协同优化策略,通过对解码关键子模块进行分析,从比特流解码、解码运算部分、播放控制3个方面来实现软件算法的优化,从而加快音频解码速度,减少存储空间,并根据优化结果对嵌入式RISC微处理器核进行配置.在现场可编程门阵列(field programmable gate ar-ray,FPGA)验证平台上实现了对128 kbps,44.1 kHz双声道AAC低复杂度框架(low complexity profile,LC)的实时解码,运算量为25.51 MIPS,优化率为48.9%.
In order to reduce hardware cost and implement advanced audio coding (AAC) based on reduced instruction set computer (RISC) processor at a lower frequency, a hardware and software co-optimization strategy is proposed. Decoding key sub-module for analysis, from three aspects of bitstream decoding, decoding operation, playback control to achieve the optimization of the software algorithm to speed up the audio decoding speed, reduce storage space, and according to the results of the optimization of embedded RISC microprocessor core To implement real-time decoding of the low complexity profile (LC) of a 128-kbps, 44.1-kHz two-channel AAC on a field programmable gate ar- ray (FPGA) verification platform, The quantity is 25.51 MIPS, the optimization rate is 48.9%.