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利用65nm CMOS制造工艺下的随机掺杂涨落(RDF)模型,建立起随机路径延时模型,通过修改台积电(TSMC)65nm低k电介质工艺器件模型库参数,完成了仲裁器型PUF电路的设计和评估。实验在Synopsys Hspice C-2010模拟设计平台上完成,测量了PUF电路的片间差异和片内差异参数,评估了128位PUF电路的性能。与实测电路参数的对比结果证明了该方法的有效性。
The stochastic path-delay model was built by using random doping fluctuation (RDF) model in 65nm CMOS fabrication process. The design of arbiter-type PUF circuit was completed by modifying TSMC 65nm low-k dielectrics device model library parameters And evaluation. Experiments were performed on the Synopsys Hspice C-2010 analog design platform. The inter-chip differences and on-chip differential parameters of the PUF circuits were measured to evaluate the performance of 128-bit PUF circuits. The comparison with the measured circuit parameters proves the effectiveness of the method.