采用 0 .1 8μm/ 1 .8V1 P6 M数字 CMOS工艺设计并实现了一种用于高性能 32位 RISC微处理器的 6 4 kb四路组相联片上高速缓冲存储器 (cache) .当采用串行访问方式时 ,该四路组相联 cache的功耗比采用传统并行访问方式在 cache命中时降低 2 6 % ,在 cache失效时降低 35 % .该 cache的设计中还采用了高速电路模块如高速电流灵敏放大器和分裂式动态 tag比较器等来提高电路工作速度 .电路仿真结果显示 cache命中时从时钟输入到数据输出的延时为 2 .7ns A 64-kbyte, four-way, on-chip cache for high-performance 32-bit RISC microprocessors was designed and implemented using a 0.18μm / 1.8V1 P6 M digital CMOS process. Row access mode, the power consumption of the four-way associative cache is reduced by 26% when the cache hit by conventional parallel access and by 35% when the cache is invalidated. The cache design also uses a high-speed circuit module such as High-speed current-sense amplifier and split dynamic tag comparator to improve circuit speed.The circuit simulation results show that the cache hit from the clock input to the data output delay of 2. .7ns