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设计了一种宽频率范围的CMOS锁相环(PLL)电路,通过提高电荷泵电路的电流镜镜像精度和增加开关噪声抵消电路,有效地改善了传统电路中由于电流失配、电荷共享、时钟馈通等导致的相位偏差问题。另外,设计了一种倍频控制单元,通过编程锁频倍数和压控振荡器延迟单元的跨导,有效扩展了锁相环的锁频范围。该电路基于Dongbu HiTek 0.18μm CMOS工艺设计,仿真结果表明,在1.8 V的工作电压下,电荷泵电路输出电压在0.25~1.5 V变化时,电荷泵的充放电电流一致性保持很好,在100 MHz~2.2 GHz的输出频率内,频率捕获时间小于2μs,稳态相对相位误差小于0.6%。
A wide frequency range CMOS phase locked loop (PLL) circuit is designed. By improving the current mirror accuracy of the charge pump circuit and increasing the switching noise cancellation circuit, the traditional circuit is effectively improved due to current mismatch, charge sharing, clock Feedthrough caused by the phase deviation problems. In addition, a multiplier control unit is designed, which effectively extends the frequency locking range of the PLL by programming the PLL multiplier and the voltage-controlled oscillator delay transconductance unit. The circuit is designed based on the Dongbu HiTek 0.18μm CMOS technology. The simulation results show that the charge-discharge current consistency of the charge pump keeps good at the output voltage of the charge pump circuit varies from 0.25 to 1.5 V at the operating voltage of 1.8 V, MHz to 2.2 GHz output frequency, the frequency acquisition time is less than 2μs, steady-state relative phase error of less than 0.6%.