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介绍了一种包含LDE效应的深亚微米电路设计流程。分析了100nm以下工艺节点LDE效应对器件的影响,以及传统集成电路设计方法的局限性。在此基础上,提出了包含LDE效应的电路设计方法,并通过中芯国际先进工艺节点的模拟电路设计实例进行了验证。结果表明,在亚100nm工艺节点,尤其在40/45nm及以下节点,LDE效应的影响已不可忽略,需要采用含LDE效应的电路设计流程。
A deep submicron circuit design flow with LDE effect is introduced. The influence of the LDE effect at 100nm process node on the device is analyzed, and the limitations of the traditional IC design method are analyzed. Based on this, a circuit design method including LDE effect was proposed and verified by simulating circuit design examples of SMIC’s advanced process nodes. The results show that the influence of LDE effect can not be neglected at sub-100nm node, especially at 40 / 45nm and below, and the circuit design flow with LDE effect is required.