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M·Core 结构是32位负载、存储 RISC 结构含固定的16位指令和优化指令集的编译程序,提供大容量存储器存储。另外,极小的、高性能的核具有单一的功率保存和高性能实时异常处理特性。该款处理器的特性包括16路通用寄存器文件,32位内部地址总线和数据总线和一个高效4级全联锁执行管道。由于具有一个桶形移位器和优良的比特字节操作能力,所以该款 M·Core 结构非常适用于小的、集成无线通信、汽车电子、消费电子和一般市场应用方案。优化的1.8V 和工业领先的 MIPS/每瓦特性,使 M·Core 控制器成为尖端低功耗RISC 技术的代表。
The M-Core architecture is a 32-bit load that holds a compiler of RISC architecture with fixed 16-bit instructions and optimized instruction set to provide mass memory storage. In addition, a very small, high-performance core has a single power-save and high-performance real-time exception handling feature. Features include 16 general purpose register files, a 32-bit internal address bus and data bus, and an efficient 4-stage full interlocked execution pipeline. With a barrel shifter and excellent bit-byte operability, the M · Core architecture is ideal for small, integrated wireless communications, automotive electronics, consumer electronics and general-purpose market applications. Optimized 1.8V and industry-leading MIPS / Watt features make M · Core controllers the cutting edge low-power RISC technology.