Ⅲ-Ⅴ compound semiconductor,due to its high mobility,is considered as one of the highly promising candidates for beyond-silicon low power logic and future high speed applications.Nanowires(NWs)with their inherent 3D cross-sections can greatly reduce the short channel effects that currently limit the scalability and linearity of various type of transistors.Generally,vertical array-based Ⅲ-Ⅴ nanowire transistors have been the focus because of the preferred nanowire growth direction by the vapor-liquid-solid(VLS)method;however,the out-of-plane geometry prevents high-speed operation because of the severe inherent parasitic capacitance and defect-free nanowire structures without massive stacking faults are challenging to grow.To address these issues,we have developed a selective lateral epitaxy(SLE)method using MOCVD,where the NWs self-assemble along certain crystal directions in plane with the substrate surface,instead of from the substrate up [1,2,3].The NWs grow out of Au nanoparticles seeds only,thus the selectivity,via the VLS mechanism.By patterning the Au nanoparticles,site-controlled perfectly parallel arrays of planar NWs can be formed.Their planar and self-aligned nature makes these in-plane NWs completely compatible with large scale manufacturing of NW-based integrated nanoelectronics.Here we present the growth mechanism,doping characterization,and device DC and RF performance of planar GaAs and InAs nanowire array MESFETs,MOSFETs,and HEMTs,using the selective lateral epitaxy method.