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提出了一种带时间延迟积分功能的高性能CMOS读出电路芯片适用的高效率电荷延迟线结构。基于该结构,设计了一款288×4规格焦平面阵列组件适用的CMOS读出电路芯片,并已完成流片、测试。该芯片包括4个视频输出端,每个端口的像元输出频率为4~5MHz(如用于实现384×288规模的成像,帧频可达160Hz)。测试结果表明这款芯片具有高动态范围(大于78dB)、高线性度(大于99.5%)、高均匀性(大于96.8%)等特征。
A high efficiency charge delay line architecture for high performance CMOS readout chip with time delay integration is proposed. Based on this structure, a CMOS readout circuit chip designed for a 288 × 4 Focal Plane Array device was designed and completed. The chip includes four video outputs, each port pixel output frequency of 4 ~ 5MHz (such as used to achieve the size of 384 × 288 imaging, frame rate up to 160Hz). Test results show that the chip features high dynamic range (greater than 78dB), high linearity (greater than 99.5%), high uniformity (greater than 96.8%) and so on.