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本论文的目的是用简单的解析式表示MOSLSI中内部引线,晶体管源,漏寄生电阻效应,并反映在MOSLSI电路/版图设计中。对于寄生电阻的解析式原来是相当复杂的。只有依靠用运用电路解析程序的电子计算机来计算的。但在本文中把源、漏寄生电阻效应用MOS晶体管的漏电流—漏电压的线性近似,就能简单地表示出来。进一步若假定上述近似在实际的LSI中成立,则由引线电阻所产生的延迟时间,就可用简单的解析式表示。用其结果对于在LSI中经常使用的交叉,得到最佳化的设计指南。源漏寄生电阻效应的解析结果同用MOS晶体管的实验结果相比取得良好的一致性,由引线电阻所产生的延迟时间的解析结果也同用环形振荡器的实验结果取得良好的一致性。从而表明两种解析结果是合适的。
The purpose of this paper is to represent the internal leads, transistor sources, parasitic resistance effects in MOSLSI with simple analytical expressions and to reflect them in the MOSLSI circuit / layout design. The analytical equation for parasitic resistance turned out to be rather complicated. Only rely on the use of circuit analysis program to calculate the computer. However, in this paper, the source and drain parasitic resistance effect MOS transistor leakage current - leakage linear approximation can be simply expressed. Further, assuming that the above approximation is true in an actual LSI, the delay time due to the lead resistance can be expressed in a simple analytical form. The result is optimized for design crossovers that are frequently used in LSIs. The analytical results of the parasitic parasitic resistance effect of the source drain have good agreement with the experimental result of the MOS transistor, and the analysis result of the delay time caused by the lead resistance also obtains good consistency with the experimental result of the ring oscillator. This shows that two analytical results are suitable.