对于传输延迟小于1ns的低功耗高速逻辑门,线路设计和制造都要求最佳参数。重要的是,这些线路中的集成三极管要求基极渡越时间短、基极电阻低以及电容小。可以肯定,离子注入是制造分离晶体管的一种可靠工具。并且这种手段将用于发展中的电路技术。本文将研究氧化物隔离的亚毫微秒逻辑门的速度、功耗与双注入晶体管(基极—硼,发射极—砷)特性的关系。为了比较,对双扩散晶体管(发射极—磷)和普通的PN结隔离线路也要给予评价,门的传输延迟与功耗关系的计算(图5)是用修正了的艾伯-莫尔(Ebrs-Moll) For low-power high-speed logic gates with propagation delays of less than 1ns, the best parameters are required for circuit design and manufacturing. Importantly, the integrated transistors in these lines require a shorter base transit time, lower base resistance, and lower capacitance. To be sure, ion implantation is a reliable tool for making isolated transistors. And this approach will be used in the development of circuit technology. This article examines the relationship between the speed and power consumption of an oxide isolated sub-nanosecond logic gate and the characteristics of a dual-injection transistor (base-boron, emitter-arsenic). For the sake of comparison, the double diffused transistor (emitter-phosphorus) and ordinary PN junction isolation circuit should also be evaluated. The calculation of gate delay and power consumption (Figure 5) is based on the modified Abel-Moore Ebrs-Moll)