【摘 要】
：
为了提高AES算法中IP核数据的吞吐量并同时减小硬件资源的占用,以达到速度和面积的折中实现,采用混合流水线结构和可重构技术完成了IP核的设计.该设计包括在同一个混合流水线
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为了提高AES算法中IP核数据的吞吐量并同时减小硬件资源的占用,以达到速度和面积的折中实现,采用混合流水线结构和可重构技术完成了IP核的设计.该设计包括在同一个混合流水线结构的流程中实现了AES算法的加密和解密过程;根据有限域的性质,对AES算法中的Sbox盒进行了优化;结合可重构技术,完成了对AES轮变换的主要构件ShiftRow和MixColumn的优化.本设计在Xilinx Virtex2p xc2vp20-7 FPGA器件上完成,其数据吞吐量达到2.58 Gbit/s,所需组合逻辑仅为3 233块,通过与同型号器件上的其他设计进行对比,实现了速度和面积的折中,在吞吐量和面积上都得到了比较理想的结果.
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