动态频率和电压调整,时钟门控以及“低功耗模式”是目前用以降低芯片和微控制器功耗的一些方法,更加新的方法正在完成之中。把数目不断增加的晶体管和越来越高的性能挤到尺寸越来越小的芯片级产品(和嵌入式微处理器)中去,正揭示了一个亟待解决的功耗问题。随着硅器件产品不断缩小到90纳米、65纳米甚至更小的处理节点时,不是运行速度而是能耗成为了性能瓶颈。 Dynamic frequency and voltage scaling, clock gating, and “low-power mode” are some of the current ways to reduce the power consumption of chips and microcontrollers. More new methods are in the works. Squeezing an ever-increasing number of transistors and ever-higher performance into smaller and smaller chip-scale products (and embedded microprocessors) is revealing a power-hungry issue. As silicon devices continue to shrink to 90 nanometers, 65 nanometers or even smaller processing nodes, not speed but energy consumption has become a performance bottleneck.