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经过工业调查,本文指出了用于各种数字电路枝术如晶体管——晶体管逻辑电路(TTL)、发射极耦合逻辑电路(ECL)和金属——氧化物——半导体电路(MOS)等的电路集成的未来水平。制版技术和材料缺乏的各种限制因素使晶片的尺寸局限于大约0.150吋×0.150吋的范围内,欲达到高度集成,必须探用引线连接法、梁式引线连接法或倒装连接法。同时,也讨论了对用线绕式或选择布线法作为互连方法的综合薄片工厂的集成水平的估计。为了得到可靠的电路工作,必须解决由于高度集成而出现的附加的装配和封装问题。
After an industrial survey, this paper identifies circuits for various digital circuit techniques such as transistor-transistor logic (TTL), emitter-coupled logic (ECL) and metal-oxide-semiconductor circuits Integrated future level. Various limitations of platemaking technology and material limitations limit the size of the wafer to approximately 0.150 inch by 0.150 inch. To achieve high integration, lead bonding, beam lead bonding or flip-chip bonding must be used. At the same time, the level of integration at the integrated wafer fab that uses wire-wound or selective routing as the interconnect method is also discussed. In order to get reliable circuit work, the additional assembly and packaging issues that arise due to the high degree of integration must be addressed.