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嵌入式微处理器是近年来国内研究的热点之一,如何以合适的成本实现高效的硬件除法单元是其中的一个技术难点。针对嵌入式微处理器设计的要求,介绍一种基于标准部件的整数除法器。电路用1个标准64位加法器、3个64位寄存器和3个64位多路选择器为主体实现非写回除法算法,在0.09μm工艺下以全定制方法实现的数据通道部分仿真时延为0.92 ns。另外,针对多周期数字系统的基本结构之一硬件循环结构介绍一种逻辑优化方法。
Embedded microprocessor is one of the hot spots in domestic research in recent years. How to realize the efficient hardware division unit with suitable cost is one of the technical difficulties. Aiming at the requirements of embedded microprocessor design, an integer divider based on standard components is introduced. Circuit with a standard 64-bit adder, three 64-bit registers and three 64-bit multiplexer as the main non-write-back algorithm to achieve full customization of the 0.09μm process in the data channel to achieve partial simulation delay 0.92 ns. In addition, a logical optimization method is introduced for the hardware cycle structure of a basic structure of a multi-cycle digital system.