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在65 nm工艺下实现了最大纠正84 bit错误的带循环冗余码(CRC)校验保护功能的BCH(32767,16416)纠错电路,纠错能力可配置。该设计采用频率比为1∶4的两种工作时钟,最高工作频率为100 MHz和400 MHz。两种工作频率的合理组合降低译码运算的延迟,提高固态硬盘读写数据的性能,同时提供了分时复用的可能。通过复用伴随式计算、关键方程系数求解(iBM算法)和钱搜索过程中的有限域乘法运算单元优化芯片面积。通过调整钱搜索的起始位置,实现编码和伴随式计算的求余电路复用,实现面积和功耗的优化,最终芯片面积节省了27%,功耗降低了26%。
The BCH (32767, 16416) error correction circuit with CRC error correction and maximum correction of 84 bit errors is realized at 65 nm with error correction capability configurable. The design uses two working clocks with a frequency ratio of 1: 4 and a maximum operating frequency of 100 MHz and 400 MHz. A reasonable combination of the two operating frequencies reduces the latency of decoding operations and improves the performance of SSDs for reading and writing data, while providing the possibility of time-division multiplexing. Optimization of the chip area is achieved by means of companion syndrome calculation, key equation coefficient solution (iBM algorithm) and finite field multiplication unit in the money search process. By adjusting the starting position of the money search, the spare circuits for encoding and companion calculation are multiplexed to achieve area and power optimization, resulting in a chip area saving of 27% and a power consumption reduction of 26%.