在设计由各种触发器组成的数字电路时,很好地掌握触发器的逻辑时序特性是十分重要的。例如,选用的触发器是用时钟脉冲的正跳变沿触发,还是用负跳变沿触发;时钟脉冲持续期间,允许不允许输入信号发生变化等等。不搞清楚这些问题,就会造成设计上的错误。本文以上无十九厂生产的TTL集成电路Z 63型JK触发器为例,讨论一下怎样分析触发器 When designing a digital circuit composed of various flip-flops, it is important to have a good grasp of the logic timing characteristics of the flip-flop. For example, whether the selected flip-flop is triggered by a positive transition of the clock pulse or by a negative transition edge, the input signal is not allowed to change during the duration of the clock pulse, and so on. If we do not understand these problems, we will create a design mistake. In this paper, no more than 19 factory production of TTL Z63 type JK trigger circuit, for example, to discuss how to analyze the trigger