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用MOS(金属氧化物半导体)结构的C-V(电容-电压)特性来研究Si-SiO_2界面的质量,是一个已为大家熟知的方法。流行的作法是在氧化好的Si片上金属化铝制作MOS电容,然后测量此MOS电容的C-V特性。此法的优点是能模拟MOS器件工艺条件,对MOS系统作一般性质的研究,并能进行BT(温度偏压)应力试验,以研究SiO_2内的可动电荷,缺点是难以区分金属化前后对系统沾污的影响,而且手续甚繁。我们采用了在一根
It is a well-known method to study the quality of the Si-SiO 2 interface by using the C-V (Capacitance-Voltage) characteristic of a MOS (Metal Oxide Semiconductor) structure. It is a popular practice to metallize aluminum on a well-oxidized Si wafer to make a MOS capacitor and measure the C-V characteristic of this MOS capacitor. The advantage of this method is that it can simulate the process conditions of MOS devices, study the general properties of MOS system, and can carry out BT (temperature bias) stress test to study the movable charges in SiO_2. The disadvantage is that it is difficult to distinguish between pairs System contamination, and the procedure is very complicated. We have adopted one