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动态绝缘栅场效应晶体管(IGFET)双稳电荷读出放大器的分析指出,最佳的自锁(Iatching)波形是一个初始阶跃电平后面接着斜率逐渐增加的斜坡电压。自锁建立时间近似反比于非平衡的初始电压。在截止边不通导时,触发器两端的容性耦合也对截止边产生一个过冲电压。用10V自锁斜坡,截止边的过冲电压典型值约为2V,而且对于0.5V的初始非平衡电压,大约在75 ns内达到充分自锁。若允许截止边有微小的通导,那末自锁时间可减小两倍或更多。其代价是在截止边增加零点几伏的过冲电压。用计算机作电路模拟证实了这个分析推导。
Analysis of a bistable charge sense amplifier in an Insulated Gate Field Effect Transistor (IGFET) states that the optimum Iatching waveform is a ramp voltage with an initial step level followed by a gradual increase in slope. The self-locking setup time is approximately inversely proportional to the unbalanced initial voltage. When the cut-off edge is not conductive, the capacitive coupling across the trigger also produces an overshoot voltage to the cut-off edge. With a 10V self-locking ramp, the cut-off edge overshoot voltage is typically around 2V, and full self-latching is achieved in approximately 75 ns for a 0.5V initial unbalanced voltage. If the cut-off edge is allowed to have small conduction, then the self-locking time can be reduced twice or more. At the expense of increasing the overshoot voltage by a few tenths of a volt at the cut-off edge. Computer simulations confirm the analysis derived.